The present invention relates to the field of semiconductor interconnect metallurgy; more specifically, it relates to a conformal barrier layer for copper interconnect metallurgy and methods of fabricating the layer.
Advanced semiconductor technology utilize copper interconnect metallurgy for wiring of active devices into integrated circuits. Typically interconnect metallurgy is formed by a damascene or dual damascene process. Damascene processes allow for very narrow, high (greater than 1), aspect ratio (height divided by width) high-density wiring features. In a damascene process, a trench is etched into a dielectric layer. A layer of conductor of sufficient thickness to fill the trench is deposited and then a chemical-mechanical-polish (CMP) process performed to remove the conductor deposited on the surface of the dielectric layer. After CMP, only the layers filling the trench remain, the surface of the filled trench being flush with the surface of the dielectric layer. In damascene technology, various interconnect levels are connected by vias independently formed in intervening dielectric layers. In dual damascene technology, the vias are integrally formed in the same dielectric as the conductive wire.
Copper has become the conductor metallurgy of choice because its high conductivity allows for higher currents in the narrower wiring features than could be achieved with older, aluminum based interconnect metallurgy. While copper provides improved electro-migration and mechanical stress reliability, copper is usually used with a redundant conductor, such as tantalum in the form of a thin layer lining the bottom and sidewalls of the trench for improved reliability. However, tantalum is not deposited directly on such dielectrics as silicon oxides because it will form beta-phase tantalum. Beta-phase tantalum has a resistivity of about 200 micro-ohms per centimeter, much too high to be of use as a redundant conducing layer. Further, copper and tantalum generally require an adhesion promotion layer when used with silicon oxide dielectrics. One material used with tantalum and copper as an adhesion promoter is tantalum nitride. When tantalum is deposited on top of tantalum nitride, alpha-phase tantalum is formed. Alpha-phase tantalum has a resistivity of about 12 to 20 micro-ohms per centimeter. Additionally, tantalum nitride acts as a copper diffusion barrier. Copper can change the characteristics of active silicon devices and its migration through the dielectric layers into the silicon must be prevented. This is not only a concern with silicon oxide dielectrics, but is a very strong concern when low-K dielectrics, such as SILK(trademark) (Dow Corning, Midland, Mich.) are used because of the porous nature of low-K materials.
However, by having a resistivity of about 250 to 500 micro-ohm per centimeter, tantalum nitride not a very good conductor. This high resistively becomes increasingly important as the density of interconnects increases and the wire size decreases with 0.25 micron and sub 0.25 micron groundrules. For a trench 0.225 microns wide and deep and a tantalum nitride layer of 25 to 50 nanometers, the tantalum nitride accounts for 30% to 56% of the cross-sectional area of the wire, partially negating the advantages gained due to the increased conductivity of copper. Further, as the aspect ratio of the trench increases the point is reached where only a narrow strip of copper can fit between the sidewalls of the trench, if indeed, the copper can be made to fill the remaining opening at all.
Therefore, there is a need for very thin tantalum nitride layer to be used as a liner in tantalum and tantalum/copper interconnect metallurgy and for a method of fabricating such very thin tantalum nitride layers.
A first aspect of the present invention is an interconnect for a semiconductor device, comprising: a conductive core having sidewalls and a bottom; and an ultra-thin layer disposed on the sidewalls and the bottom of said conductive core.
A second aspect of the present invention is a method of forming an ultra-thin tantalum nitride layer comprising: providing a tantalum target; initiating an inert gas plasma and flowing nitrogen into the plasma for a predetermined period of time to sputter tantalum nitride onto a substrate; and after expiration of the fixed period of time, stopping the flow of nitrogen.
A third aspect of the present invention is a method of forming an ultra-thin tantalum nitride layer comprising: providing a tantalum target; precharging the tantalum target with nitrogen by flowing nitrogen over the tantalum target; and initiating an inert gas plasma to sputter tantalum nitride onto a substrate.
A fourth aspect of the present invention is a method for fabricating an interconnect for a semiconductor device, comprising: forming a dielectric layer on a semiconductor substrate; forming a trench in the dielectric layer; placing the semiconductor substrate in a plasma deposition chamber having a tantalum target; initiating a plasma in the presence of nitrogen in the plasma deposition chamber; and depositing an ultra-thin layer comprising tantalum and nitrogen in the trench.